羅中泉教授Chung-Chuan Lo
RESEARCH INTERESTS
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Neural decision-making models神經決策模型
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Spatial orientation and working memory models空間方向和工作記憶模型
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Connectome連接組
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Fruit fly behavior neuroscience果蠅行為神經科學
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Neuromorphic Engineering神經形態工程
Selected Publication
Frontiers in Neuroinformatics
Yu-Chi Huang, Cheng-Te Wang, Ta-Shun Su, Kuo-Wei Kao, Yen-Jen Lin, Chao-Chun Chuang, Ann-Shyn Chiang and Chung-Chuan Lo* (2019). A Single-Cell Level and Connectome-Derived Computational Model of the Drosophila Brain. Frontiers in Neuroinformatics 12:99
Nature Communications
Ta-Shun Su, Wan-Ju Lee, Yu-Chi Huang, Cheng-Te Wang and Chung-Chuan Lo* (2017). Coupled symmetric and asymmetric circuits underlying spatial orientation in fruit flies. Nature Communications 8:139
Frontiers in Neuroinformatics
Po-Yen Chang, Ta-Shun Su, Chi-Tin Shih* and Chung-Chuan Lo* (2017). The Topographical Mapping in Drosophila Central Complex Network and its Signal Routing. Frontiers in Neuroinformatics 11:26.
PLOS Computational Biology
Chung-Chuan Lo* and Xiao-Jing Wang* (2016). Conflict Resolution as Near-Threshold Decision-Making: A Spiking Neural Circuit Model with Two-Stage Competition for Antisaccadic Task. PLOS Computational Biology 12:8
謝志成教授Chih-Cheng Hsieh
RESEARCH INTERESTS
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CMOS imaging sensor ICCMOS成像傳感器積體電路
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SAR ADC & Sigma-delta modulator (SDM)SAR ADC和Sigma-Delta調製器（SDM）
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Smart Image sensor智能影像感應器
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Analog & mixed-mode IC模擬混合模式積體電路
Selected Publication
ISSCC
Tzu-Hsiang Hsu*, Yen-Kai Chen*, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, “A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel,” ISSCC Dig. Tech. Papers, Feb. 2020 (Accepted)
Sung-En Hsieh and Chih-Cheng Hsieh, “A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator,” ISSCC Dig. Tech. Papers, Feb. 2018.
JSSC
Kwuang-Han Chang and Chih-Cheng Hsieh, “A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps,” in IEEE Journal of Solid-State Circuits, vol. 54, no. 10, pp. 2691-2702, Oct. 2019.
Kwuang-Han Chang and Chih-Cheng Hsieh, “A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors,” IEEE Journal of Solid- State Circuits, vol 54, no. 6, pp. 1624-1635, June. 2019.
Sung-En Hsieh, and Chih-Cheng Hsieh, “A 0.4 V 13-bit 270 kS/s SAR-ISDM ADC with Opamp-Less Time-Domain Integrator,” IEEE Journal of Solid-State Circuits, vol 54, no. 6, pp. 1648-1686, June. 2019.
Albert Yen-Chih Chiou, and Chih-Cheng Hsieh, “An ULV PWM CMOS Imager with Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting,” IEEE Journal of Solid-State Circuits, vol 54, no. 1, pp. 298-306, Jan. 2019.
ISSCC Forum Talk
2018 "Nano-Watt Ultra-Low-Voltage SAR ADC Design"
2019 "ADCs for Biomedical and IoT Applications"
IEDM Invited Talk
2019 "AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device"
鄭桂忠教授Kea-Tiong Tang
RESEARCH INTERESTS
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Neuromorphic circuit神經形態電路
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AI accelerator人工智慧加速器
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Electronic Nose電子鼻
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Neuroprosthetics神經義肢
Selected Publication
JXCDC 2020
Wei-Chen Wei et. al., “A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random-Access Memory (ReRAM)-based Computing-In-Memory”, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 6 (1), pp. 45-52, June 2020.
IEEE Sensors Journal 2020
Syuan-He Wang et. al., “Using a Hybrid Deep Neural Network for Gas Classification”, IEEE Sensors Journal, Vol. 21 (5), pp. 6401-6407, November 2020.
Electronic Letters
Meysam Akbari et. al., “A 0.3-V adjustable current winner-take-all circuit for analog neural networks”, Electronic Letters, accepted.
VLSI 2019
Kea-Tiong Tang et. al., “Considerations of Integrating Computing-In-Memory and Processing-In-Sensor into Convolutional Neural Network Accelerators for Low-Power Edge Devices”, 2019 Symposia on VLSI Technology and Circuits (VLSI 2019), Kyoto, Japan. (EI)
ISSCC 2020
Tzu-Hsiang Hsu et. al., “A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel,” 2020 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
張孟凡教授Meng-Fan Chang
RESEARCH INTERESTS
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Memory Integrated Circuits記憶體積體電路設計
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Computing-in-Memory (Processing-in-Memory) Circuits記憶體內運算電路設計
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Memristor-based Neuromorphic Circuits for Artificial Intelligence仿生人工智慧晶片之憶阻器電路設計
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Memory-based Circuits for Security and Blockchains用於安全性和區塊鏈的記憶體電路
Selected Publication
Nature Electronics
W. -H. Chen, et al., "CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors. " Nature Electronics, vol.2, no.9, pp.420-428, Sept. 2019
ISSCC
X. Si, et al., " A Twin-8T SRAM Computation-In-Memory Macro for Multiple-bits CNN-Based Machine Learning, ” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 396-398, Feb. 2019
ISSCC
C. -X. Xue, et al., " A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing time for CNN-based AI Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 388-390, Feb. 2019
ISSCC
T. -C. Chang, et al., " A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read-Bandwidth for Security-Aware Mobile Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb. 2020 (Accepted)
呂仁碩教授Ren-Shuo Liu
RESEARCH INTERESTS
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Computer architecture and systems計算機架構和系統
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Memory hierarchy記憶體層級
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Non-volatile memory systems非揮發記憶體系統
Selected Publication
ASP-DAC 2021
Jun-Shen Wu, Chi-En Wang, Ren-Shuo Liu*, Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators, Asia and South Pacific Design Automation Conference (ASP-DAC '21), Virtual Conference, Jan.18-21, 2021
ESSCIRC 2019
Yun-Chen Lo, Yu-Chun Kuo, Yun-Sheng Chang, Jian-Hao Huang, Jun-Shen Wu, Wen-Chien Ting, Tai-Hsing Wen, and Ren-Shuo Liu*, Physically-Tightly-coupled, Logically-Loosely-coupled, Near-Memory BNN Accelerator (PTLL-BNN),” European Solid-State Circuits Conference (ESSCIRC ’19), Krakow, Poland, Sep. 23-26, 2019
ATC 2019
Yun-Sheng Chang and Ren-Shuo Liu*, “OPTR: Order-Preserving Translation and Recovery Design for SSDs with a Standard Block Device Interface,” USENIX Annual Technical Conference (ATC '19), Renton, USA, Jul. 10-12, 2019. (acceptance rate: 71/356=19.9%)
ASP-DAC 2018
Ren-Shuo Liu* and Jian-Hao Huang, “DI-SSD: Desymmetrized Interconnection Architecture and Dynamic Timing Calibration for Solid-State Drives,” Asia and South Pacific Design Automation Conference (ASP-DAC '18), Jeju, Korea, Jan. 22-25, 2018
ICCAD 2017
Ren-Shuo Liu*, Yun-Sheng Chang, and Chih-Wen Hung, “VST: A Virtual Stress Testing Framework for Discovering Bugs in SSD Flash-Translation Layers,” International Conference on Computer-Aided Design (ICCAD '17), Irvine, USA, Nov. 13-17, 2017